Insulated gate bipolar transistor, semiconductor device, method of manufacturing insulated-gate bipolar transistor, and method of manufacturing semiconductor device

ABSTRACT

An insulated gate bipolar transistor, a semiconductor device using such a transistor, and manufacturing methods of these. The transistor, device, and method eliminate the necessity of connection to a freewheel diode used for bypassing a circulating current. In the transistor, device, and method the concentration of impurities of an N+ buffer layer that forms a junction with a P+ collector layer is increased so that it is possible to reduce an avalanche breakdown voltage of a parasitic diode formed by an N base layer and the P+ collector layer. Thus, the reverse voltage resistance of an IGBT is lowered to not more than 5 times the collector-emitter saturated voltage.

TECHNICAL FIELD

The present invention relates to an insulated gate bipolar transistor, amanufacturing method of such a transistor, a semiconductor device usingsuch an insulated gate bipolar transistor and a manufacturing methodthereof.

BACKGROUND ART

In a power semiconductor device for driving a load such as a motor, aninsulated gate bipolar transistor (referred to simply as an IGBT) isused in a rated voltage area of not less than 300 V as a switchingelement installed therein so as to provide a better characteristic. Inthis case, a circulating diode parallel-connected to the switchingelement is used at the same time.

FIG. 29 is a front cross-sectional view that shows a conventional IGBT.This IGBT 151 comprises a semiconductor substrate 90 having first andsecond major surfaces. This semiconductor substrate 90, which is asilicon substrate, comprises a P⁺ collector layer 91 that is a P⁺substrate exposed to the first major surface, an N⁺ buffer layer 92formed thereon, an N⁻ base layer 93 that is formed thereon, and has alower concentration of impurities than the N⁺ buffer layer 92, a P baseregion 2 that is formed by selectively diffusing P-type impurities onthe second major surface to which the N⁻ base layer 93 is exposed, andan N⁺ source region 3 that is formed as a shallower region than the Pbase region 2 by selectively diffusing N-type impurities with a highconcentration inside this P base region 2.

On the second major surface of the semiconductor substrate 90 is formeda gate insulating film 4 made of a silicon dioxide in a manner so as tocover one portion of a surface of P the base region 2 and a surface ofthe N⁻ base layer 93. A gate electrode 5 made of polysilicon is formedon the gate insulating film 4. On the upper major surface of thesemiconductor substrate 90, an emitter electrode 7 is further formed soas to connect one portion of the surface of the N⁺ source region 3 and acenter area of the surface of the P base region 2. The gate electrode 5and the emitter electrode 7 are insulated from each other by aninterlayer insulating film 6.

Therefore, the N⁻ base layer 93, the P base region 2 and the N⁺ sourceregion 3, which are formed on the second major surface side of thesemiconductor substrate 90, correspond to a semiconductor portion of anMOS transistor. The portion having the same structure as the MOStransistor, which is formed on the second major surface of thesemiconductor substrate 90, is referred to as an MOS structure M. Aportion of the surface of the P base region 2, which is located rightbelow the gate electrode 5, and sandwiched by the source region 3 andthe N⁻ base layer 93, that is, a portion at which the gate electrodes 5face each other with the gate insulating film 4 sandwiched in between,corresponds to a channel region CH of the MOS structure M. The P baseregion 2 and the N⁺ source region 3 are formed by selectively implantingand diffusing impurities by using the gate electrode 5 as a mask. Thatis, since the P base region 2 and the N⁺ source region 3 form a doublediffusion region, the MOS structure M forms one example of a DoubleDiffused MOS (referred to simply as a DMOS). A collector electrode 8 tobe connected to the P⁺ collector layer 91 is formed on the first majorsurface of the semiconductor substrate 90.

FIG. 30 is a front cross-sectional view of an insulated gate bipolartransistor in accordance with another conventional example. This IGBT151a is typically different from IGBT151 in its MOS structure M formed onthe second major surface side of the semiconductor substrate 90. Atrench 9, which penetrates an N⁺ source region 3 and a P base region 2to reach an N⁻ base layer 93, is formed on the second major surface, anda gate insulating film 4 is formed in a manner so as to cover the innerwall face thereof. Moreover, a gate electrode 5 is buried inside thegate insulating film 4. In this IGBT151 a also, a portion of a surfaceof the P base region 2 (which includes a surface exposed to the trench9), which is sandwiched by the N⁺ source region 3 and an N⁻ base layer93, that is, a portion at which the gate electrodes 5 face each otherwith the gate insulating film 4 sandwiched in between, corresponds to achannel region CH of an MOS transistor.

In this manner, each of the planar IGBT151 of FIG. 29 and thetrench-type IGBT151 a of FIG. 30 comprises the P⁺ collector layer 91that is exposed to the first major surface of the semiconductorsubstrate 90, the N base layers 92, 93 formed thereon, the MOS structureM (including one portion of the N⁻ base layer 93) formed on the secondmajor surface and the collector electrode 8 that is formed on the firstmajor surface and connected to the P⁺ collector layer 91. Normally, anumber of cells, shown in FIGS. 29 and 30, are reciprocally arrangedalong the major surfaces of the semiconductor substrate 90 so that agreater current rate is obtained by this arrangement. In FIG. 29, onecell is drawn, and in FIG. 30, two cells are drawn.

Next, the operations of IGBT151 and 151 a will be described. In thestructures of FIGS. 29 and 30, with a predetermined collector-emittervoltage (referred to as a collector voltage) V_(CE) being appliedbetween the emitter electrode 7 and the collector electrode 8, agate-emitter voltage (referred to as a gate voltage) V_(GE) with apositive bias having a predetermined level is applied between theemitter electrode 7 and the gate electrode 5; that is, upon turning onthe gate, the conductive type of the channel region CH is inverted froma P type to an N type. As a result, a channel serving as a carrier pathis formed in the channel region CH. Electrons are injected from theemitter electrode 7 to the N⁻ base layer through this channel. Theelectrons thus injected make the P⁺ collector layer 91 and the N baselayers 92, 93 forwardly biased so that holes are injected to the N baselayers 92, 93 from the P⁺ collector layer 91. As a result, theresistance of the N⁻ base layer 92 drops greatly so that the currentcapacity of the IGBT151, 151 a is increased.

Next, when the gate voltage V_(GE) is set from a positive bias value to0 or a reverse bias value, that is, when the gate is turned off, thechannel region CH, inverted to the N type, is restored to the P type.Consequently, the injection of electrons from the emitter electrode 7 isstopped. The stop of injection of electrons also stops the injection ofholes from the P⁺ collector layer 91. Thereafter, electrons and holes,accumulated in the N base layers 92, 93, are either drawn into thecollector electrode 8 and the emitter electrode 7, respectively, orrecombined with each other to disappear.

Next, a description will be given of a semiconductor device as a typicalapplied apparatus of the conventional IGBTs151 and 151 a. FIG. 31 is acircuit diagram (in which 151 is typically added as a reference numberfor an IGBT) of a semiconductor device using the IGBTs151, 151 a asswitching elements. This semiconductor device 152 is formed as athree-phase inverter. Freewheel diodes 160 are parallel-connected to sixIGBTs151, respectively. Freewheel diodes 160 are connected in such adirection that the reverse current of the corresponding IGBT151 isbypassed. The parallel connection in this direction is also referred toas “reverse parallel connection”.

With respect to six IGBTs151, every two of them are series-connected.The collector electrode 8 of one of two series-connected IGBTs151 isconnected to a higher potential power-supply terminal PP, and theemitter electrode 7 of the other is connected to a lower potentialpower-supply terminal NN. That is, three series circuits, each havingtwo IGBTs151, are connected in parallel with each other between thehigher potential power-supply terminal PP and the lower potentialpower-supply terminal NN. An external d-c power-supply 20 is connectedto the higher potential power supply terminal PP and the lower potentialpower-supply terminal NN so as to supply a direct-current voltage. Ineach of the series circuits, a connected portion of two IGBTs151series-connected is connected to any one of output terminals U, V, W.For example, a load 21 of, for example, a three-phase motor is connectedto the three-phase output terminals U, V, W. A gate voltage V_(GE) isexternally applied to each of six gate electrodes 5 placed in sixIGBTs151 individually so that six IGBTs151 are selectively turn on andoff. Thus, three-phase alternating currents are supplied to the load 21.Here, a single-phase inverter, constituted by removing one of the threeseries circuits from the semiconductor device 152 of FIG. 31, has beenconventionally used.

FIG. 32 is a plan view of a conventionally-known semiconductor devicethat shows a specific construction of the semiconductor device (that is,a three-phase inverter) of FIG. 31, and FIG. 33 is a cross-sectionalview of the semiconductor device taken along a cutting line X—X of FIG.32. The circuit diagram of this semiconductor device 153 is shown inFIG. 31. The semiconductor device 153 comprises a housing 130, aheat-radiating plate 131 formed as one portion thereof, a substrate 135placed on the heat-radiating plate 131, the six IGBTs151 placed on thesubstrate 135, the six freewheel diodes 160 also placed on the substrate135, the higher potential power-supply terminal PP, the lower potentialpower-supply terminal NN, the three output terminals U, V, W, the sixgate terminals G, a plurality of conductive wires w and a lid 133.

The housing 130 (including the heat-radiating plate 131) and the lid 133cooperatively form a closed space 132, and the substrate 135 is mountedin this closed space 132. Each of the higher potential power-supplyterminal PP, the lower potential power-supply terminal NN, the threeoutput terminals U, V, W, and the six gate terminals G, is buried in thehousing 130 so that its upper end portion protrudes from an upperportion of the housing 130, and its lower end portion is exposed to theclosed space 132. The six IGBTs151 and the six freewheel diodes 160 areconnected to the eleven terminals PP, NN, U, V, W, G through a number ofconductive wires w. The conductive wires w are, for example, aluminumwires. Here, FIG. 32 shows the semiconductor device 153 with its lid 133removed.

FIG. 34 is a plan view of the substrate 135, and also shows the IGBTs151and the freewheel diodes 160 placed thereon. The substrate 135 comprisesan insulating plate 136 and wiring patterns 137 placed thereon. Theinsulating plate 136 is fixed on the heat-radiating plate 131 (FIG. 33),and the IGBT151 and the freewheel diode 160 are mounted onto the wiringpattern 137, and electrically connected thereto. In this manner, both ofthe IGBT151 and the freewheel diode 160 are used in the form of a bearchip.

The collector electrode 8 of each IGBT151 is connected to the cathodeelectrode of the corresponding freewheel diode 160 through the wiringpattern 137. The emitter electrode 7 of each IGBT151 and the anodeelectrode of the corresponding freewheel diode 160 are connected to eachother through the conductive wire w. Moreover, the emitter electrode 7of one of the two IGBTs151 constituting a series circuit and the higherpotential power-supply terminal PP are connected to each other by theconductive wire w, and the emitter electrode 7 of the other and any oneof the three output terminals U, V, W, the collector electrode 8 of theone and any one of the three output terminals U, V, W, and the collectorelectrode 8 of the other and the lower potential power-supply terminalNN are respectively connected to each other by the wiring pattern 137and the conductive wire w. Moreover, the respective gate electrodes 5 ofthe six IGBTs151 and the corresponding gate terminals G are connected toeach other by the conductive wires w.

FIG. 35 is an inner perspective view of a semiconductor device thatshows another example of an applied apparatus. This semiconductor device154 comprises a heat-radiating plate 125, an IGBT151 and a freewheeldiode 160 that are placed thereon, a collector terminal 121, an emitterterminal 122, a gate terminal 123, conductive wires w and a sealingmember 126 that seals all the elements except for the tip portions ofthe respective three terminals 121, 122, 123. A heat-radiating plate125, which is made of cupper, and also referred to as a cupper frame,serves as a reinforcing member and a wiring pattern as well.

The collector electrode 8 of the IGBT151 is connected to the cathodeelectrode of the corresponding freewheel diode 160 and the collectorterminal 121 through the heat-radiating plate 125. The emitter electrode7 of the IGBT151 and the anode electrode of the corresponding freewheeldiode 160 are connected to each other by the conductive wire w.Moreover, the emitter electrode 7 of the IGBT151 and the emitterterminal 122 are connected to each other by the conductive wire w, andthe gate electrode 5 of the IGBT151 and the gate terminal 123 are alsoconnected to each other by the conductive wire w.

As shown in FIGS. 31 to 33, in the case when an inductive load such as amotor is connected to the conventional IGBT151 (or 151 a in the samemanner), the freewheel diode 160 has been required so as to bypass acirculating current that forms a reverse current to the IGBT151. Aninductive component included in the impedance of the inductive load (forexample, represented by an induction L) stores energy in a magneticfield generated by a current. Therefore, a change in the current flowingthrough the induction L corresponds to a change in the energy to bestored. During the process in which the current flowing through theinductive load is interrupted, the induction L is exerted in such a wayas to interrupt the change in current. Energy, accumulated in theinduction L, is released to the IGBT151 that serves as a switchingelement to interrupt the current so that the current flowing through theinduction L is attenuated.

The energy accumulated in the induction L is so great that, if releasedinstantaneously, it might easily break the IGBT151. Therefore, duringthe process in which the IGBT151 is turned off, the current flowingthrough the inductive load is circulated by bypassing it to thefree-wheel diode 160 so that the current flowing through the inductiveload is not changed by the switching. In the semiconductor device 152 ofFIG. 31, when one of the IGBTs151, which has been turned on toelectrically connect the direct-current power supply 20 to the load 21and supply a power-supply voltage to the load 21, is turned off, thecurrent flowing through the load 21 is made to pass through thefreewheel diode 160 and reversely flow through the direct-current powersupply 20 by energy stored in the induction L of the load 21. As aresult, a direct-current voltage that is reversed equivalently isapplied to the load 21.

By changing the ratio between the time in which the IGBT151 is on andthe time in which it is off, the ratio between the period in which thepower-supply voltage of the direct-current power supply 20 is applied inthe forward direction and the period in which it is applied in thereverse direction is changed so that it is possible to control theaverage voltage to be applied to the load 21. Thus, by allowing thisratio to change in a sine-wave form, it is possible to supply to theload 21 a smooth alternating current without abruptly turning on or offthe current flowing through the load 21 in synchronism with switching ofthe IGBT151.

The inverter such as the semiconductor device 152 carries out theabove-described operation so that, as shown in FIGS. 31 to 33, it isnecessary to connect the freewheel diode 160 in reverse-parallel to thecorresponding IGBT151. A power MOSFET, which has been used as aswitching element since before the appearance of the IGBT151, inherentlyhas a structure having a built-in reverse-parallel diode; therefore, ithas been not necessary to connect the freewheel diodes 160 thereto in aseparated manner. However, the power MOSFET has only a low currentdensity, and is not suitable for the application with a great current.

In contrast, the IGBT, which is suitable for the application with agreat current, and has a construction in which an N⁺ layer of the powerMOSFET is replaced with the P⁺ collector layer 91 so that a parasiticdiode is formed between the P⁺ collector layer 91 on the collectorelectrode 8 side and the N⁻ base layers 92, 93. This tends to functionas a high barrier with respect to a circulating current. The breakdownvoltage of the parasitic diode is approximately 30 to 50 V, and this isan excessively high value so as to use the parasitic diode as asubstitute for the reverse-parallel-connected freewheel diode. For thisreason, if the freewheel diode 160 is not connected, IGBT151 might bedamaged due to heat generated by a reverse voltage generated at the timeof the circulation.

As described above, although the conventional IGBTs151, 151 a aresuperior to the power MOSFETs in that the current density is great, theyneed to be connected to the freewheel diodes 160 when they are applied,and this causes extra costs and makes the structure of a semiconductordevice serving as an application device complex, resulting in anincrease in the size, an increase in the number of parts used forconnections as well as an increase in processing costs.

DISCLOSURE OF INVENTION

The present invention has been devised to solve the above-mentionedproblems, and an object thereof is to provide an insulated gate bipolartransistor which can eliminate the necessity of connection to afreewheel diode, a semiconductor device using such a transistor, andmanufacturing method thereof.

In order to achieve this object, the first aspect of the presentinvention is related to an insulated gate bipolar transistor comprisinga semiconductor substrate having first and second major surfaces, acollector electrode which is located on said first major surface side ofthe semiconductor substrate, and an emitter electrode and a gateelectrode that are located on said second major surface side, whereinthe semiconductor substrate comprises a collector layer of a firstconductive type that is exposed to the first major surface and connectedto the collector electrode, and a base layer of a second conductive typethat is formed on the collector layer and is not exposed to the firstmajor surface, and wherein the base layer and the collector layer have acharacteristic as a free-wheel diode.

The second aspect of the present invention, which relates to aninsulated gate bipolar transistor in accordance with the first aspect,wherein a reverse voltage resistance, which is a minimum value of acollector-emitter voltage when a reverse current flows between theemitter electrode and the collector electrode, is set to not more than 5times a collector-emitter saturated voltage.

The third aspect of the present invention, which relates to an insulatedgate bipolar transistor in accordance with the second aspect, isdesigned so that the base layer comprises a base main body portion and abuffer layer that has a higher concentration of impurities than the basemain body portion and is interpolated between the collector layer andthe base main body portion, and a minimum value of a collector-emittervoltage when an avalanche current flows through a parasitic diode formedby the base layer and the collector layer is equivalent to the reversevoltage resistance.

The fourth aspect of the present invention, which relates to theinsulated gate bipolar transistor in accordance with the second aspect,is designed so that the semiconductor substrate further comprises areverse conductive-type layer of the second conductive type that isformed inside the collector layer so as not to be connected to the baselayer, and selectively exposed to the first major surface, and connectedto the collector electrode, and a minimum value of a collector-emittervoltage, that causes a punch through in which a depletion layergenerated in a PN junction between the base layer and the collectorlayer reaches the reverse conductive-type layer, is equivalent to thereverse voltage resistance.

The fifth aspect of the present invention, which relates to theinsulated gate bipolar transistor in accordance with the fourth aspect,is designed so that the collector layer comprises a low impurityconcentration collector layer, and a high impurity concentrationcollector layer, the low impurity concentration collector layercomprises a portion of the collector layer sandwiched by the base layerand the reverse conductive-type layer, and the high impurityconcentration collector layer has a concentration of impurities higherthan the low impurity concentration collector layer.

The sixth aspect of the present invention, which relates to theinsulated gate bipolar transistor in accordance with the fourth aspect,is designed so that the base layer comprises a base main body portion,and a buffer layer that has a higher concentration in impurities thanthe base main body portion, and is interpolated between the collectorlayer and the base main body portion.

The seventh aspect of the present invention, which relates to theinsulated gate bipolar transistor in accordance with the second aspect,is designed so that the semiconductor substrate further comprises areverse conductive-type layer of the second conductive type that isformed inside the collector layer so as not to be connected to the baselayer, and selectively exposed to the first major surface and connectedto the collector electrode, and a minimum value of a collector-emittervoltage when a parasitic bipolar transistor formed by the base layer,the collector layer and the reverse conductive type layer turns on, isequivalent to the reverse voltage resistance.

The eighth aspect of the present invention, which relates to theinsulated gate bipolar transistor in accordance with the seventh aspect,is designed so that the collector layer comprises a low impurityconcentration collector layer, and a high impurity concentrationcollector layer, and the low impurity concentration collector layercomprises a portion of the collector layer sandwiched by the base layerand the reverse conductive-type layer, and the high impurityconcentration collector layer has a concentration of impurities higherthan the low impurity concentration collector layer.

The ninth aspect of the present invention, which relates to theinsulated gate bipolar transistor in accordance with the seventh aspect,is designed so that the base layer comprises a base main body portion,and a buffer layer that has a higher concentration in impurities thanthe base main body portion, and is interpolated between the collectorlayer and the base main body portion.

The tenth aspect of the present invention, which relates to theinsulated gate bipolar transistor in accordance with the second aspect,is designed so that the reverse voltage resistance is not more than 10V.

In accordance with the eleventh aspect of the present invention, asemiconductor device comprises the insulated gate bipolar transistor inaccordance with the first aspect, a housing in which the insulated gatebipolar transistor is mounted, and three terminals each of which isattached to said housing with its one portion protruding from saidhousing toward the exterior, and which are electrically connected tosaid gate electrode, said emitter electrode and said collector electrodeof the insulated gate bipolar transistor, respectively.

In accordance with the twelfth aspect of the present invention, thesemiconductor device which relates to the eleventh aspect is designed sothat the gate electrode, the emitter electrode and the collectorelectrode are electrically connected to the three terminals throughconductive wires, respectively.

The thirteenth aspect of the present invention, which relates to thesemiconductor device in accordance with the eleventh aspect, furthercomprises the insulated gate bipolar transistor serving as a firsttransistor, three insulated gate bipolar transistors having the samestructure as the first transistor and serving as second through fourthtransistors, the three-terminals serving as first to third terminals,and five terminals each of which is attached to the housing with oneportion thereof protruding from the housing toward the exterior, thefive terminals serving as fourth to eighth terminals, wherein the firstand second transistors are series-connected, the third and fourthtransistors are series-connected, the first terminal is electricallyconnected to the collector electrodes of the first and thirdtransistors, the second terminal is electrically connected to connectingsections of the first and second transistors, the third terminal iselectrically connected to the gate electrode of the first transistor,the fourth terminal is electrically connected to the emitter electrodesof the second and fourth transistors, the fifth terminal is electricallyconnected to connecting sections of the third and fourth transistors,and the sixth through eighth terminals are electrically connected to thegate electrodes of the second through fourth transistors, respectively.

The fourteenth aspect of the present invention, which relates to thesemiconductor device in accordance with the thirteenth aspect, furthercomprises an inductive load connected to the second terminal and thefifth terminal.

The fifteenth aspect of the present invention, which relates to asemiconductor device, comprises the insulated gate bipolar transistor inaccordance with the first aspect, a sealing member that seals theinsulated gate bipolar transistor, and three terminals each of which issealed by the sealing member with one portion thereof protruding fromthe sealing member toward the exterior, the three terminals electricallyconnected to the gate electrode, the emitter electrode and the collectorelectrode of the insulated gate bipolar transistor, respectively.

In accordance with the sixteenth aspect of the present invention, amanufacturing method of an insulated gate bipolar transistor whichcomprises a semiconductor substrate having first and second majorsurfaces, a collector electrode that is located on the first majorsurface side of the semiconductor substrate, and an emitter electrodeand a gate electrode that are located on the second major surface side,comprising the steps of: (a) forming the semiconductor substrate so asto provide a collector layer of a first conductive type that is exposedto the first major surface and a base layer of a second conductive typethat is formed on the collector layer and is not exposed to the firstmajor surface, and (b) forming the collector electrode on the firstmajor surface so as to be connected to the collector layer, wherein inthe step (a), the semiconductor substrate is formed so that the baselayer and the collector layer are allowed to have a characteristic as afreewheel diode.

The seventeenth aspect of the present invention, which relates to themanufacturing method of an insulated gate bipolar transistor inaccordance with the sixteenth aspect, is designed so that in the step(a), the semiconductor substrate is formed in such a manner that areverse voltage resistance, which is a minimum value of acollector-emitter voltage when a reverse current flows between theemitter electrode and the collector electrode, is set to not more than 5times the collector-emitter saturated voltage.

The eighteenth aspect of the present invention, which relates to themanufacturing method of an insulated gate bipolar transistor inaccordance with the seventeenth aspect, is designed so that in the step(a), the base layer comprises a base main body portion and a bufferlayer that has a higher concentration in impurities than the base mainbody portion and is interpolated between the collector layer and thebase main body portion, and the semiconductor substrate is formed sothat a minimum value of a collector-emitter voltage when an avalanchecurrent flows through a parasitic diode formed by the base layer and thecollector layer is equivalent to the reverse voltage resistance.

The nineteenth aspect of the present invention, which relates to themanufacturing method of an insulated gate bipolar transistor inaccordance with the seventeenth aspect, is designed so that in the step(a), the semiconductor substrate further comprises a reverseconductive-type layer of the second conductive type that is formedinside the collector layer so as not to be connected to the base layer,and selectively exposed to the first major surface, and connected to thecollector electrode, and the semiconductor substrate is formed so that aminimum value of a collector-emitter voltage that causes a punch throughin which a depletion layer generated in a PN junction between the baselayer and the collector layer reaches the reverse conductive-type layeris equivalent to the reverse voltage resistance.

The twentieth aspect of the present invention, which relates to themanufacturing method of the insulated gate bipolar transistor inaccordance with the nineteenth aspect, is designed so that in theabove-mentioned step (a), the collector layer comprises a low impurityconcentration collector layer and a high impurity concentrationcollector layer, and in the semiconductor substrate thus formed, the lowimpurity concentration collector layer includes a portion of thecollector layer sandwiched by the base layer and the reverseconductive-type layer, and the high impurity concentration collectorlayer has a concentration of impurities higher than the low impurityconcentration collector layer.

The twenty-first aspect of the present invention, which relates to themanufacturing method of the insulated gate bipolar transistor inaccordance with the nineteenth aspect, is designed so that in the step(a), the semiconductor substrate is formed in such a manner that thebase layer comprises a base main body portion and a buffer layer thathas a higher concentration in impurities than the base main bodyportion, and is interpolated between the collector layer and the basemain body portion.

The twenty-second aspect of the present invention, which relates to themanufacturing method of an insulated gate bipolar transistor inaccordance with the seventeenth aspect, is designed so that in the step(a), the semiconductor substrate further comprises a reverseconductive-type layer of the second conductive type that is formedinside the collector layer so as not to be connected to the base layer,and selectively exposed to the first major surface, and connected to thecollector electrode, and the semiconductor substrate is formed so that aminimum value of a collector-emitter voltage when a parasitic bipolartransistor formed by the base layer, the collector layer and the reverseconductive type layer turns on is equivalent to the reverse voltageresistance.

The twenty-third aspect of the present invention, which relates to themanufacturing method of the insulated gate bipolar transistor inaccordance with the twenty-second aspect, is designed so that in thestep (a), the semiconductor substrate is formed in such a manner thatthe collector layer comprises a low impurity concentration collectorlayer and a high impurity concentration collector layer, and in thisstructure, the low impurity concentration collector layer includes aportion of the collector layer sandwiched by the base layer and thereverse conductive-type layer, and the high impurity concentrationcollector layer has a concentration of impurities higher than the lowimpurity concentration collector layer.

The twenty-fourth aspect of the present invention, which relates to themanufacturing method of the insulated gate bipolar transistor inaccordance with the twenty-second aspect, is designed so that in thestep (a), the semiconductor substrate is formed in such a manner thatthe base layer comprises a base main body portion and a buffer layerthat has a higher concentration in impurities than the base main bodyportion, and is interpolated between the collector layer and the basemain body portion.

The twenty-fifth aspect of the present invention, which relates to themanufacturing method of the insulated gate bipolar transistor inaccordance with the seventeenth aspect, is designed so that in the step(a), the semiconductor substrate is formed in such a manner that thereverse voltage resistance is set to not more than 10 V.

In the twenty-sixth aspect of the present invention, a manufacturingmethod of a semiconductor device comprises the steps of: (A) obtaining ahousing having three terminals each of which is attached thereto withits one portion protruding toward the exterior, (B) executing themanufacturing method of the insulated gate bipolar transistor accordingto claim 16 to thereby obtain the insulated gate bipolar transistor, (C)mounting the insulated gate bipolar transistor in the housing, and (D)electrically connecting the three terminals to the gate electrode, theemitter electrode and the collector electrode of the insulated gatebipolar transistor, respectively.

In the twenty-seventh aspect of the present invention that relates tothe manufacturing method of the semiconductor device in accordance withthe twenty-sixth aspect, the step (D) further comprises a step (D-1) ofelectrically connecting the gate electrode, the emitter electrode andthe collector electrode to the three terminals respectively throughconductive wires.

In the twenty-eighth aspect of the present invention that relates to themanufacturing method of the semiconductor device in accordance with thetwenty-sixth aspect, the step (A) is arranged so that the housing isobtained with the three-terminals serving as the first to thirdterminals, and allowed to further include five terminals each of whichis attached thereto with its one portion externally sticking out as thefourth through eighth terminals; the step (B) is arranged so that theinsulated gate bipolar transistor is obtained as the first transistorwith three insulated gate bipolar transistors having the same structureas the first transistor being obtained as the second through fourthtransistors; the step (C) is arranged so that, in addition to the firsttransistor, the second through fourth transistors are mounted in thehousing; and the step (D) further comprises the steps of: (D1)connecting the first and second transistors in series with each other;(D2) connecting the third and fourth transistors in series with eachother; (D3) electrically connecting the first terminal to the collectorelectrodes of the first and third transistors; (D4) electricallyconnecting the second terminal to the connecting sections of the firstand second transistors; (D5) electrically connecting the third terminalto the gate electrode of the first transistor; (D6) electricallyconnecting the fourth terminal to the emitter electrodes of the secondand fourth transistors; (D7) electrically connecting the fifth terminalto the connecting sections of the third and fourth transistors; and (D8)electrically connecting the six through eighth terminals to the gateelectrodes of the second through fourth transistors.

In the twenty-ninth aspect of the present invention, the manufacturingmethod of the semiconductor device in accordance with the twenty-eighthaspect further comprises a step of (E) connecting an inductive load tothe second terminal and the fifth terminal.

In the thirtieth aspect of the present invention, a manufacturing methodof a semiconductor device comprises the steps of: (A) obtaining threeterminals, (B) executing the manufacturing method of the insulated gatebipolar transistor according to claim 16 to thereby obtain the insulatedgate bipolar transistor, (C) electrically connecting the three terminalsto the gate electrode, the emitter electrode and the collector electrodeof the insulated gate bipolar transistor, respectively, and (D) sealingthe insulated gate bipolar transistor and the three terminals in such amanner that one portion of each of the three terminals is allowed toprotrude toward the exterior.

The present invention, which has the arrangements as described above,makes it possible to provide the following effects.

In accordance with the insulated gate bipolar transistor related to thefirst aspect of the present invention, since the base layer and thecollector layer have the characteristic of the freewheel diode, it isnot necessary to externally connect the freewheel diode upon applicationthereof.

In accordance with the insulated gate bipolar transistor related to thesecond aspect of the present invention, since the reverse voltageresistance is reduced to not more than 5 times the collector-emittersaturated voltage, the circulating current is allowed to flow throughitself without the necessity of any special heat-radiating design evenwhen an inductive load is connected thereto.

In accordance with the insulated gate bipolar transistor related to thethird aspect of the present invention, since the reverse voltageresistance is determined by the avalanche breakdown of the parasiticdiode, it is possible to easily suppress the collector-emitter saturatedvoltage to a low level by increasing the concentration of impurities ofthe collector layer. Moreover, since the buffer layer is installed, itis possible to make the base layer thinner, and consequently to furtherreduce both of the collector-emitter saturated voltage and the reversevoltage resistance.

In accordance with the insulated gate bipolar transistor related to thefourth aspect of the present invention, since the reverseconductive-type layer is formed inside the collector layer, the reversevoltage resistance is determined by a punch through voltage, and itbecomes possible to set the reverse voltage resistance to a low level.

In accordance with the insulated gate bipolar transistor related to thefifth aspect of the present invention, since the collector layercomprises the high impurity concentration collector layer, it becomespossible to suppress the collector-emitter saturated voltage to a lowlevel by compensating for the reduction in the amount of injection ofholes due to the installed reverse conductive-type layer.

In accordance with the insulated gate bipolar transistor related to thesixth aspect of the present invention, since the buffer layer isinstalled, it is possible to make the base layer thinner, andconsequently to further reduce both of the collector-emitter saturatedvoltage and the reverse voltage resistance.

In accordance with the insulated gate bipolar transistor related to theseventh aspect of the present invention, since the reverseconductive-type layer is formed inside the collector layer, the reversevoltage resistance is determined by a turning-on of the parasiticbipolar transistor so that it becomes possible to easily set the reversevoltage resistance to a low level.

In accordance with the insulated gate bipolar transistor related to theeighth aspect of the present invention, since the collector layercomprises the high impurity concentration collector layer, it becomespossible to suppress the collector-emitter saturated voltage to a lowlevel by compensating for the reduction in the amount of injection ofholes due to the installed reverse conductive-type layer.

In accordance with the insulated gate bipolar transistor related to theninth aspect of the present invention, since the buffer layer isinstalled, it is possible to make the base layer thinner, andconsequently to further reduce both of the collector-emitter saturatedvoltage and the reverse voltage resistance.

In accordance with the insulated gate bipolar transistor related to thetenth aspect of the present invention, since the reverse voltageresistance is set to not more than 10 V, it is possible to reduce theamount of heat generation due to the reverse current to a low level,even in the case of a collector-emitter saturated voltage exceeding 2 V.

In accordance with a semiconductor device related to the eleventh aspectof the present invention, since the insulated gate bipolar transistor ismounted in a housing, it is possible to provide a convenient means inwhich the insulated gate bipolar transistor is connected to a powersupply and a load and utilized. Moreover, since the insulated gatebipolar transistor in accordance with the first aspect of the presentinvention that requires no freewheel diodes is utilized, it is possibleto miniaturize the device, and also to cut manufacturing costs.

In accordance with the semiconductor device related to the twelfthaspect of the present invention, since each electrode of the insulatedgate bipolar transistor and each terminal are electrically connectedthrough the conductive wire, it is possible to simplify themanufacturing process, and consequently to further reduce themanufacturing cost. In particular, since no freewheel diodes arerequired, it is possible to reduce the number of conductive wires andthe number of connecting processes.

In accordance with the semiconductor device related to the thirteenthaspect of the present invention, since the insulated gate bipolartransistor in accordance with the first aspect of the present inventionthat requires no freewheel diodes is utilized, it is possible to achievea small-size inverter that is inexpensive and easily used.

In accordance with the semiconductor device related to the fourteenthaspect of the present invention, since an inductive load is connected,it is possible to drive the inductive load by only connecting a directcurrent supply and a control circuit.

In accordance with the semiconductor device related to the fifteenthaspect of the present invention, since the insulated gate bipolartransistor is sealed by the sealing member, it is possible to provide aconvenient means in which the insulated gate bipolar transistor isconnected to a power supply and a load and utilized. Moreover, since theinsulated gate bipolar transistor in accordance with the first aspect ofthe present invention that requires no freewheel diodes is utilized, itis possible to miniaturize the device, and also to cut manufacturingcosts.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the sixteenth aspect of the presentinvention, since the base layer and collector layer are allowed to havethe characteristic as the freewheel diode, it is possible to obtain theinsulated gate bipolar transistor that requires no externally connectedfreewheel diode upon application thereof.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the seventeenth aspect of the presentinvention, since the reverse voltage resistance is reduced to not morethan 5 times the collector-emitter saturated voltage, it is possible toprovide the insulated gate bipolar transistor in which the circulatingcurrent is allowed to flow through itself without the necessity of anyspecial heat-radiating design even when an inductive load is connectedthereto.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the eighteenth aspect of the presentinvention, since the semiconductor substrate is formed so that thereverse voltage resistance is determined by the avalanche breakdown ofthe parasitic diode, it is possible to easily suppress thecollector-emitter saturated voltage to a low level by increasing theconcentration of impurities of the collector layer. Moreover, since thebuffer layer is installed, it is possible to make the base layerthinner, and consequently to further reduce both of thecollector-emitter saturated voltage and the reverse voltage resistance.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the nineteenth aspect of the presentinvention, since the semiconductor substrate is formed so that thereverse conductive-type layer is formed inside the collector layer andthe reverse voltage resistance is consequently determined by a punchthrough voltage, it becomes possible to set the reverse voltageresistance to a low level.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the twentieth aspect of the presentinvention, since the semiconductor substrate is formed so that thecollector layer comprises the high impurity concentration collectorlayer, it becomes possible to suppress the collector-emitter saturatedvoltage to a low level by compensating for the reduction in the amountof injection of holes due to the installed reverse conductive-typelayer.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the twenty-first aspect of the presentinvention, since the buffer layer is installed, it is possible to makethe base layer thinner, and consequently to further reduce both of thecollector-emitter saturated voltage and the reverse voltage resistance.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the twenty-second aspect of the presentinvention, since the semiconductor substrate is formed so that thereverse conductive-type layer is formed inside the collector layer withthe reverse voltage resistance being determined by a turning-on of theparasitic bipolar transistor, it becomes possible to easily set thereverse voltage resistance to a low level.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the twenty-third aspect of the presentinvention, since the semiconductor substrate is formed so that thecollector layer has the high impurity concentration collector layer, itbecomes possible to suppress the collector-emitter saturated voltage toa low level by compensating for the reduction in the amount of injectionof holes due to the installed reverse conductive-type layer.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the twenty-fourth aspect of the presentinvention, since the buffer layer is installed, it is possible to makethe base layer thinner, and consequently to further reduce both of thecollector-emitter saturated voltage and the reverse voltage resistance.

In accordance with the manufacturing method of the insulated gatebipolar transistor related to the twenty-fifth aspect of the presentinvention, since the reverse voltage resistance is set to not more than10 V, it is possible to reduce the amount of heat generation due to thecirculating current to a low level, even in the case of thecollector-emitter saturated voltage exceeding 2 V.

In accordance with the manufacturing method of the semiconductor devicerelated to the twenty-sixth aspect of the present invention, since theinsulated gate bipolar transistor is mounted in the housing, it ispossible to provide the convenient means in which the insulated gatebipolar transistor is connected to a power supply and a load andutilized. Moreover, since the insulated gate bipolar transistor inaccordance with the first aspect of the present invention that requiresno freewheel diodes is utilized, it is possible to miniaturize thedevice, and also to cut manufacturing costs.

In accordance with the manufacturing method of a semiconductor devicerelated to the twenty-seventh aspect of the present invention, sinceeach electrode of the insulated gate bipolar transistor and eachterminal are electrically connected through the conductive wire, it ispossible to simplify the manufacturing process, and consequently tofurther reduce the manufacturing cost. In particular, since no freewheeldiodes are required, it is possible to reduce the number of conductivewires and the number of connecting processes.

In accordance with the manufacturing method of the semiconductor devicerelated to the twenty-eighth aspect of the present invention, since theinsulated gate bipolar transistor in accordance with the first aspect ofthe present invention that requires no freewheel diodes is utilized, itis possible to achieve a small-size inverter that is inexpensive andeasily used.

In accordance with the manufacturing method of a semiconductor devicerelated to the twenty-ninth aspect of the present invention, since theinductive load is connected, it is possible to provide the semiconductordevice that can drive the inductive load by only connecting a directcurrent supply and a control circuit.

In accordance with the manufacturing method of the semiconductor devicerelated to the thirtieth aspect of the present invention, since theinsulated gate bipolar transistor is sealed by the sealing member, it ispossible to provide the convenient semiconductor device in which theinsulated gate bipolar transistor is connected to a power supply and aload, and utilized. Moreover, since the insulated gate bipolartransistor in accordance with the first aspect of the present inventionthat requires no freewheel diodes is utilized, it is possible tominiaturize the device, and also to cut manufacturing costs.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a front cross-sectional view of an IGBT in accordance with afirst preferred embodiment.

FIG. 2 is a front cross-sectional view of another example of IGBT inaccordance with the first preferred embodiment.

FIGS. 3 and 4 are descriptive drawings that show the construction of theIGBT in accordance with the first preferred embodiment.

FIG. 5 is a graph that describes the construction of the IGBT inaccordance with the first preferred embodiment.

FIGS. 6 and 7 are drawings that show manufacturing processes in amanufacturing method of the IGBT in accordance with the first preferredembodiment.

FIG. 8 is a drawing that shows a manufacturing process in anothermanufacturing method of the IGBT in accordance with the first preferredembodiment.

FIG. 9 is a front cross-sectional view of an IGBT in accordance with asecond preferred embodiment.

FIG. 10 is a front cross-sectional view of another example of IGBT inaccordance with the second preferred embodiment.

FIGS. 11 and 12 are drawings that show manufacturing processes in amanufacturing method of the IGBT in accordance with the second preferredembodiment.

FIG. 13 is a drawing that shows a manufacturing process in anothermanufacturing method of the IGBT in accordance with the second preferredembodiment.

FIG. 14 is a front cross-sectional view of an IGBT in accordance with athird preferred embodiment.

FIG. 15 is a front cross-sectional view of another example of IGBT inaccordance with the third preferred embodiment.

FIG. 16 is a front cross-sectional view of an IGBT in accordance with afourth preferred embodiment.

FIG. 17 is a front cross-sectional view of another example of IGBT inaccordance with the fourth preferred embodiment.

FIG. 18 is a drawing that shows a manufacturing process in amanufacturing method of the IGBT in accordance with the fourth preferredembodiment.

FIG. 19 is a drawing that shows a manufacturing process in anothermanufacturing method of the IGBT in accordance with the fourth preferredembodiment.

FIG. 20 is a circuit diagram that shows a semiconductor device inaccordance with a fifth preferred embodiment.

FIG. 21 is a plan view that shows a semiconductor device in accordancewith a sixth preferred embodiment.

FIG. 22 is a cross-sectional view of the semiconductor device inaccordance with the sixth preferred embodiment.

FIG. 23 is a plan view that shows a substrate in accordance with thesixth preferred embodiment.

FIG. 24 is a cross-sectional view that shows the substrate in accordancewith the sixth preferred embodiment.

FIG. 25 is a perspective view that shows the semiconductor device inaccordance with the sixth preferred embodiment.

FIGS. 26, 27 and 28 are drawings that show processes in a manufacturingmethod of the semiconductor device in accordance with the sixthpreferred embodiment.

FIG. 29 is a front cross-sectional view of an IGBT in accordance with aconventional technique.

FIG. 30 is a front cross-sectional view of another example of IGBT inaccordance with the conventional technique.

FIG. 31 is a circuit diagram of a semiconductor device in accordancewith the conventional technique.

FIG. 32 is a plan view that shows another example of semiconductordevice in accordance with the conventional technique.

FIG. 33 is a cross-sectional view of another example of semiconductordevice in accordance with the conventional technique.

FIG. 34 is a plan view that shows another example of substrate inaccordance with the conventional technique.

FIG. 35 is a perspective view that shows still another example ofsemiconductor device in accordance with the conventional technique.

BEST MODE FOR CARRYING OUT THE INVENTION

1. First Preferred Embodiment

(Outline of a Device Construction)

FIG. 1 is a front cross-sectional view of an IGBT in accordance with afirst preferred embodiment of the present invention. This IGBT101comprises a semiconductor substrate 1 having first and second majorsurfaces. This semiconductor substrate 1, which is a silicon substrate,comprises a P⁺ collector layer 11 that is a P⁺ substrate that is exposedto the first major surface, an N⁺ buffer layer 12 formed thereon, an N⁻base layer 13 that is formed thereon with a lower concentration ofimpurities than the N⁺ buffer layer 12, a P base region 2 that is formedby selectively diffusing P-type impurities on the second major surfaceto which the N⁻ base layer 13 is exposed, and an N⁺ source region 3 thatis formed as a region shallower than the P base region 2 by selectivelydiffusing N-type impurities with a high concentration inside this P baseregion 2. Here, in the N⁺ buffer layer 12, the concentration of theN-type impurities is set higher than that of the N⁺ buffer layer 92 ofthe conventional IGBT151 (see FIG. 29).

A gate insulating film 4, made of a silicon dioxide, is formed on thesecond major surface of the semiconductor substrate 1 in a manner so asto cover one portion of a surface of the P base region 2 and a surfaceof the N⁻ base layer 13. A gate electrode 5, made of polysilicon, isformed on the gate insulating film 4. An emitter electrode 7 is furtherformed on the upper major surface of the semiconductor substrate 1 in amanner so as to connect with one portion of the surface of the N⁺ sourceregion 3 and a center area of the surface of the P base region 2. Thegate electrode 5 and the emitter electrode 7 are insulated from eachother by an interlayer insulating film 6.

Therefore, the N⁻ base layer 13, the P base region 2 and the N⁺ sourceregion 3, which are formed on the second major surface side of thesemiconductor substrate 1, correspond to a semiconductor portion of anMOS transistor. In the same manner as the IGBT151, 151 a, the portionhaving the same construction as the MOS transistor formed on the secondmajor surface side of the semiconductor substrate 1 is referred to as anMOS construction M. A portion of the surface of the P base region 2,which is located right below the gate electrode 5, and sandwiched by thesource region 3 and the N⁻ base layer 13, that is, a portion at whichthe gate electrodes 5 face each other with the gate insulating film 4sandwiched in between, corresponds to a channel region CH of the MOSstructure M. The P base region 2 and the N⁺ source region 3 are formedby selectively implanting and diffusing impurities by using the gateelectrode 5 as a mask. That is, since the P base region 2 and the N⁺source region 3 form a double diffusion region, the MOS structure Mforms one example of Double Diffused MOS (referred to simply as a DMOS).A collector electrode 8 to be connected to the P⁺ collector layer 11 isformed on the first major surface of the semiconductor substrate 1.

FIG. 2 is a front cross-sectional view of an insulated gate bipolartransistor in accordance with another example of the first preferredembodiment. This IGBT101 a is typically different from the IGBT101 inits MOS structure M formed on the second major surface side of thesemiconductor substrate 1. A trench 9, which penetrates an N⁺ sourceregion 3 and a P base region 2 to reach an N⁻ base layer 13, is formedon the second major surface, and a gate insulating film 4 is formed in amanner so as to cover the inner wall surface thereof. Moreover, a gateelectrode 5 is buried inside the gate insulating film 4. In this IGBTl01a also, a portion of a surface of the P base region 2 (which includes asurface exposed to the trench 9), which is sandwiched by the N⁺ sourceregion 3 and the N⁻ base layer 13, that is, a portion at which the gateelectrodes 5 face each other with the gate insulating film 4 sandwichedin between, corresponds to a channel region CH of the MOS transistor. Inthe same manner as the IGBT101, an N⁺ buffer layer 12 is set to have ahigher concentration in N-type impurities than that of the N⁺ bufferlayer 92 of the conventional IGBT151 a (FIG. 30).

In this manner, each of the planar IGBT101 of FIG. 1 and the trench-typeIGBT101 a of FIG. 2 comprises a P⁺ collector layer 11 that is exposed tothe first major surface of the semiconductor substrate 1, the N baselayers 12, 13 formed thereon, the MOS structure M (including one portionof the N⁻ base layer 13) formed on the second major surface and acollector electrode 8 that is formed on the first major surface andconnected to the P⁺ collector layer 11. A number of cells, shown in FIG.1 or 2, are reciprocally arranged along the major surfaces of thesemiconductor substrate 1 so that a greater current rate is obtained bythis arrangement. In FIG. 1, one cell is drawn, and in FIG. 2, two cellsare drawn.

(Outline of the Operation of the Device)

Next, the operations of IGBT101 and 101 a will be described. In thestructures of FIGS. 1 and 2, with a predetermined collector-emittervoltage (referred to as a collector voltage) V_(CE) being appliedbetween the emitter electrode 7 and the collector electrode 8, agate-emitter voltage (referred to as a gate voltage) V_(GE) with apositive bias having a predetermined level is applied between theemitter electrode 7 and the gate electrode 5; that is, upon turning onthe gate, a conductive type of the channel region CH is inverted from aP type to an N type. As a result, a channel serving as a carrier path isformed in the channel region CH. Electrons are injected from the emitterelectrode 7 to the N⁻ base layer through this channel. The electronsthus injected make the P⁺ collector layer 11 and the N base layers 12,13 forwardly biased so that holes are injected to the N base layers 12,13 from the P⁺ collector layer 11. As a result, the resistance of N⁻base layer 12 drops greatly so that the current capacity of IGBT101, 101a is increased.

Next, when the gate voltage V_(GE) is set from a positive bias value to0 or a reverse bias value, that is, when the gate is turned off, thechannel region CH, inverted to the N type, is restored to the P type.Consequently, the injection of electrons from the emitter electrode 7 isstopped. The stop of injection of electrons also stops the injection ofholes from the P⁺ collector layer 11. Thereafter, electrons and holes,accumulated in the N base layers 12, 13, are either drawn into thecollector electrode 8 and the emitter electrode 7, respectively, orrecombined with each other to disappear.

(Featured Construction and Featured Operation of the Device)

When the IGBT101, 101 a are in an off state, a collector voltage V_(CE),which is applied between the emitter electrode 7 and the collectorelectrode 8, is determined by a thickness of the N⁻ base layer 13 andits concentration of impurities. Moreover, in the IGBTs101, 101 a, aparasitic diode D is formed in an equivalent manner by the N base layers12, 13 and the P⁺ collector layer 11. In the N⁺ buffer layer 12, theconcentration of N-type impurities is set sufficiently higher than theN⁺ buffer layer 92 of the conventional IGBT151, 151 a; therefore, thebreakdown voltage of parasitic diode D, which is determined by the P⁺layer 11 and the N⁺ buffer layer 12, is suppressed to a low level. Thisbreakdown voltage determines the reverse voltage resistance of IGBTs101,101 a. When the reverse voltage applied between the emitter electrode 7and the collector electrode 8 exceeds the reverse voltage resistance, areverse current flows from the emitter electrode 7 to the collectorelectrode 8.

FIGS. 3 to 5 are drawings quoted from page 105 of “Semiconductor Device”written by S. M. Sze (published by “Sangyo Tosho”, in 1987)(translationof S. M. Sze, “Semiconductor Devices-Physics and Technology-”, publishedby Bell Telephone Laboratories, Inc. 1985). FIG. 3 shows a curvedsurface of a PN junction that is generated at the end portion of adiffusion mask in a planar diffusion process, and a symbol r_(j)represents a curvature radius of the curved surface. FIG. 4 shows adiffusion region that is formed by using a diffusion mask having arectangular shape, a symbol PL represents a plane region, a symbol CYrepresents a cylinder shaped region, and a symbol SP represents aspherical region. FIG. 3 corresponds to a longitudinal cross-sectionalview showing the diffusion region of FIG. 4. FIG. 5 represents therelation between the breakdown voltage V_(B) and the concentration ofimpurities N_(B) in the PN junction shown in FIGS. 3 and 4. Thebreakdown voltage V_(B) means a reverse voltage that causes an avalanchebreakdown in the PN junction.

The graph of FIG. 5 shows that it is possible to reduce the breakdownvoltage between the N⁺ buffer layer 12 and the P⁺ collector layer 11 tonot more than 10 V, by adjusting the concentration of impurities of N⁺buffer layer 12 (so as to set to not less than 5×10¹⁷ cm⁻³). A powerfactor of a normal inductive load such as a motor is set to a high levelsuch as not less than 0.8; therefore, in a normal inverter that isconnected to such an inductive load, and used, the average value ofcurrents flowing through the IGBT in a forward direction becomes notless than 5 times the average value of the circulating current.Therefore, if the reverse voltage resistance of the IGBT is set to avoltage of not more than 5 times a voltage between the collectorelectrode 8 and the emitter electrode 7 at the time when the IGBT is on,that is, no more than 5 times a collector-emitter saturated voltageV_(CE (sat)), it becomes possible to allow the circulating current topass through the IGBT itself as a reverse current without causing adamage due to heat generation, even when a freewheel diode is notconnected to the IGBT and the heat radiating structure of theconventional IGBT, as it is, is adopted. The collector-emitter saturatedvoltage V_(CE (sat)) is approximately 2 V; therefore, if the reversevoltage resistance of the IGBT can be set to not more than 10 V, itbecomes possible to use the IGBT as a switching element in an inverterwithout the necessity of freewheel diode.

The graph of FIG. 5 shows that the IGBTs101, 101 a can be designed asthe IGBT that is applicable without using the freewheel diode, bysetting the concentration of impurities in the N⁺ buffer layer 12 to asufficiently high value. The IGBTs101, 101 a having such an arrangementare allowed to function in a manner equivalent to IGBTs151, 151 a inwhich freewheel diodes, each having a forward voltage V_(F) of not morethan 10 V, are connected in reverse-parallel with each other.

(Manufacturing Method of the Device)

FIGS. 6 and 7 are manufacturing process drawings that show one exampleof a manufacturing method of the IGBT101, 101 a. In this example, first,a silicon substrate 11 of a P⁺ type is prepared (FIG. 6). Next, an N⁺buffer layer 12 and an N⁻ base layer 13 are formed in this order (FIG.7) on a major surface of the silicon substrate 11. The N⁺ buffer layer12 and the N⁻ base layer 13 may be formed by implanting and diffusingimpurities or by utilizing the epitaxial growth. A portion of thesilicon substrate 11 that is left as a P⁺ type semiconductor layer afterthe N⁺ buffer layer 12 and the N⁻ base layer 13 have been formedcorresponds to the P⁺ collector layer 11.

In the case when the epitaxial growth is utilized in both of theformation processes of the N⁺ buffer layer 12 and the N⁻ base layer 13,the silicon substrate 11, as it is, forms the P⁺ collector layer 11. Inthe case of the application of implantation and diffusion of impuritiesalso, the major portion of silicon substrate 11 forms the P⁺ collectorlayer 11. Therefore, the silicon substrate 11 is represented by the samereference number as the P⁺ collector layer 11.

Next, after the MOS structure M including one portion of the N⁻ baselayer 13 has been formed on the second major surface of thesemiconductor substrate 1, the collector electrode 8 is formed on thefirst major surface of the semiconductor substrate 1 to which the P⁺collector layer 11 is exposed (FIG. 1 or FIG. 2). Since the processesfor forming the MOS structure M have been conventionally known, thedetailed description thereof is omitted. In the processes for formingthe semiconductor substrate 1, the shape (including the size) ofrespective semiconductor layers and the concentration of impurities arecontrolled so that the reverse voltage resistance of each of theIGBTs101, 101 a is set to not more than 5 times the collector-emittersaturated voltage V_(CE(sat)), more preferably, not more than 10 V. Inparticular, the concentration of impurities of the N⁺ buffer layer 12 isadjusted. After the above-mentioned processes, the IGBTs101, 101 a havebeen completed.

FIG. 8 is a manufacturing process drawing that shows another example ofa method for manufacturing the IGBTs101, 101 a. In this example, firstan N⁻ type silicon substrate 13 is prepared. Next, an N⁺ buffer layer 12and a P⁺ collector layer 11 are formed in this order on a major surfaceof the silicon substrate 13 to form the same structure as that of FIG.7. The N⁺ buffer layer 12 and the P⁺ collector layer 11 may be formed byimplanting and diffusing impurities or utilizing the epitaxial growth.Thereafter, the above-mentioned processes for forming the MOS structureM and the collector electrode 8, which have been described by referenceto FIG. 1 or FIG. 2, are carried out to form the IGBTs101, 101 a.

A portion of the silicon substrate 13 that is left as an N⁻ typesemiconductor layer, after the N⁺ buffer layer 12, the P⁺ collectorlayer 11, the P base region 2 and the N⁺ source region 3 have beenformed, corresponds to the N⁻ base layer 13. Since the N⁻ base layer 13corresponds to the major portion of the silicon substrate 13, thesilicon substrate 13 is represented by the same reference number as theN⁻ base layer 13.

The above-mentioned processes are the same as those manufacturingprocesses of the conventional IGBTs151, 151 a, except that the shape ofthe respective semiconductor layers and the concentration of impuritiesare controlled so that the reverse voltage resistance of each of theIGBTs101, 101 a is set to not more than 5 times the collector-emittersaturated voltage V_(CE(sat)). That is, the IGBTs101, 101 a can bemanufactured without the necessity of any special complex processes incomparison with the conventional IGBTs151, 151 a.

2. Second Preferred Embodiment

FIG. 9 is a front cross-sectional view that shows an IGBT in accordancewith a second preferred embodiment of the present invention. In thefollowing drawings, those parts that are the same as or correspond to(those parts having the same functions as) those of the device inaccordance with the first preferred embodiment shown in FIG. 1 and FIG.2 are represented by the same reference numbers, and the descriptionthereof is omitted. Here, an IGBT102, shown in FIG. 9, is typicallydistinct from the IGBT101 of FIG. 1 in that the semiconductor substrate1 comprises an N⁺ reverse conductive-type layer 14 (for example,referred to as a reverse conductive-type layer, since it has aconductive type reversed to the P⁺ collector layer 11 on the peripherythereof). The N⁺ reverse conductive-type layer 14 is selectively exposedto the first major surface of the semiconductor substrate 1, and formedinside the P⁺ collector layer 11 so as to be shallower than the P⁺collector layer 11. Therefore, the N⁺ reverse conductive-type layer 14and the N base layers 12, 13 are separated from each other by the P⁺collector layer 11.

When a reverse voltage is applied between the collector electrode 8 andthe emitter electrode 7, a depletion layer DL is generated at a PNjunction of the parasitic diode D. A thickness of the P⁺ collector layer11 (in particular, a thickness of a portion making the N⁺ reverseconductive-type layer 14 and the N⁺ buffer layer 12 separate from eachother) and the concentration of impurities are adjusted so that, whenthis reverse voltage is not more than 5 times (more preferably, not morethan 10 V) the collector-emitter saturated voltage V_(CE(sat)), thedepletion layer DL is allowed to reach the N⁺ reverse conductive-typelayer 14 (that is, a punch through occurs). As a result, the reversevoltage resistance of IGBT102 is regulated by the punch through so thatthe reverse voltage resistance is set to a value not more than 5 timesthe collector-emitter saturated voltage V_(CE(sat)). Therefore, in thesame manner as the IGBTs101, 101 a of the first preferred embodiment, itbecomes possible to use the IGBT102 as a switching element in aninverter without the necessity of connection to the freewheel diode.

Even when the N⁺ reverse conductive-type layer 14 is installed, thebasic switching operation serving as the IGBT is unchanged from theoperation of conventional IGBTs151, 151 a. Since the N⁺ reverseconductive-type layer 14 is installed, the injection efficiency of holesfrom the P⁺ collector layer 11 is reduced. However, in general, a lifetime killer is introduced to the N⁻ base layer and the N⁺ buffer layer12 so that by adjusting the amount of the introduction of the life timekiller, it is possible to compensate for a change in characteristics dueto the reduction of the injection efficiency of holes.

In the IGBT102, the N⁺ buffer layer 12 does not necessarily give anessential effect to the punch through. Therefore, even in a structureform in which the N⁺ buffer layer 12 is omitted as shown as an IGBT102 ain FIG. 10, it is possible to obtain the same effect as the IGBT102 withrespect to the reverse voltage resistance. However, the IGBT102 havingthe N⁺ buffer layer 12 makes it possible to provide a thinner N⁻ baselayer 13. Moreover, although not shown in the Figures, in the samemanner as the IGBT101 a (FIG. 2) of the first preferred embodiment, theMOS structure M of the IGBT102, 102 a may be changed to a trench type,and the same effect is obtained with respect to the reverse voltageresistance.

The structure of IGBTs102, 102 a is unchanged from the structure thathas been conventionally adopted in IGBTs with high voltage resistanceand generally referred to as “non-punch through structure”, except forcharacteristics in the thickness of the P⁺ collector layer 11 and theconcentration of impurities. Therefore, in a method for manufacturingthe IGBTs12, 102 a also, the conventional method as it is may be adoptedexcept that the thickness of the P⁺ collector layer 11 and theconcentration of impurities are controlled, as will be described below.

Upon manufacturing the IGBTs102, 102 a, first, an N⁻ type siliconsubstrate 13 is prepared as shown in FIG. 8. Next, the P⁺ layer 11 isformed on one major surface of the silicon substrate 13 by carrying outa process shown in FIG. 11. The P⁺ layer 11 may be formed by implantingand diffusing impurities or utilizing the epitaxial growth. Next, asshown in FIG. 12, the N⁺ reverse conductive-type layer 14 is formed byselectively implanting and diffusing N type impurities on the majorsurface to which the P⁺ layer 11 is exposed.

When the N⁺ buffer layer 12 is formed, the N⁺ buffer layer 12 and the P⁺collector layer 11 are formed on one major surface of the siliconsubstrate 13 in this order, as shown in FIG. 13 in place of FIG. 12, andN-type impurities are then selectively implanted and diffused on themajor surface to which the P⁺ layer 11 is exposed so that the N⁺ reverseconductive-type layer 14 is formed. Both of the N⁺ buffer layer 12 andthe P⁺ collector layer 11 may be formed by implanting and diffusingimpurities or utilizing the epitaxial growth.

Upon completion of the processes shown in FIG. 12 or FIG. 13, the MOSstructure M and the collector electrode 8 are formed so that theIGBTs102, 102 a are completed (FIG. 9 or FIG. 10).

3. Third Preferred Embodiment

FIGS. 14 and 15 are front cross-sectional views of IGBTs in accordancewith the third preferred embodiment of the present invention. An IGBT103shown in FIG. 14 and an IGBT103 a shown in FIG. 15 are assembled in thesame manner as the IGBTs102 and 102 a of the second preferredembodiment, respectively, except for differences in the thickness of theP⁺ collector layer 11 and the concentration of impurities. The N baselayers 12, 13, the P⁺ collector layer 11 and the N⁺ reverseconductive-type layer 14 constitute an NPN-type parasitic bipolartransistor Q in an equivalent manner. An emitter of this parasiticbipolar transistor Q is connected to the collector electrode 8, and abase is connected to the collector electrode 8 through a resistor R. Theresistor R corresponds to a resistance component belonging to a portionof the P⁺ collector layer 11 sandwiched by the N base layers 12, 13 andthe N⁺ reverse conductive-type layer 14.

With respect to the IGBTs103, 103 a, the thickness of the P⁺ collectorlayer 11 (in particular, the thickness of a portion making the N⁺reverse conductive-type layer 14 and the N⁺ buffer layer 12 separatefrom each other) and the concentration of impurities are adjusted sothat, when a reverse voltage to be applied between the collectorelectrode 8 and the emitter electrode 7 is not more than 5 times (morepreferably, not more than 10 V) the collector-emitter saturated voltageV_(CE(sat)), a parasitic bipolar transistor Q is turned on. As a result,the reverse voltage resistance of IGBT103, 103 a is regulated byturning-on of the parasitic bipolar transistor Q, and set to a value notmore than 5 times the collector-emitter saturated voltage V_(CE(sat)).Therefore, in the same manner as the IGBT101, 101 a of the firstpreferred embodiment, the IGBT102 may be used as an inverter without thenecessity of connection to the freewheel diode.

In the IGBT103, the N⁺ buffer layer 12 does not necessarily give anessential effect to the turning-on of parasitic bipolar transistor Q.Therefore, the IGBTs103 and 103 a are allowed to mutually obtain thesame effect with respect to the reverse voltage resistance. However, theIGBT103 having the N⁺ buffer layer 12 makes it possible to provide thethinner N⁻ base layer 13. Moreover, although not shown in the Figures,in the same manner as the IGBT101 a (FIG. 2) of the first preferredembodiment, the MOS structure M of the IGBT103, 103 a may be changed toa trench type, and the same effects are obtained with respect to thereverse voltage resistance.

The structure of IGBTs103, 103 a is the same as the structure ofIGBTs102, 102 a except for characteristics in the thickness of the P⁺collector layer 11 and the concentration of impurities. Therefore, theIGBTs103, 103 a are easily manufactured by using the same processes asthe manufacturing processes of the IGBT102, 102 a. For this reason, withrespect to the manufacturing method of the IGBT103, 103 a, the detaileddescription thereof is omitted.

4. Fourth Preferred Embodiment

FIGS. 16 and 17 are front cross-sectional views of an IGBT in accordancewith the fourth preferred embodiment of the present invention. AnIGBT104 shown in FIG. 16 is characterized in that a P⁺ type diffusionlayer 15 having a high concentration of impurities is selectively formedin the P⁺ collector layer 11 of the IGBT102 in accordance with thesecond preferred embodiment or the IGBT103 in accordance with the thirdpreferred embodiment. In the same manner, an IGBT104 a shown in FIG. 17is characterized in that a P⁺ type diffusion layer 15 having a highconcentration of impurities is selectively formed in the P⁺ collectorlayer 11 of the IGBT102 a in accordance with the second preferredembodiment or the IGBT103 a in accordance with the third preferredembodiment.

In other words, in the IGBT104, 104 a, the P⁺ collector layer 11comprises a P⁺ layer 11 a having a low concentration of impurities (forexample, referred to as a “low-impurity-concentration collector layer”)and a P⁺ diffusion layer 15 having a high concentration of impurities(for example, referred to as a “high-impurity-concentration collectorlayer”). The P⁺ diffusion layer 15 is formed in a manner adjacent to theN⁺ reverse conductive-type layer 14 along the first major surface of thesemiconductor substrate 1 by selectively diffusing P-type impurities ina portion of the first major surface of the semiconductor substrate 1 towhich no N⁺ reverse conductive-type layer 14 is exposed. The P⁺ layer 11a corresponds to a portion of the P⁺ collector layer 11 having no P⁺diffusion layer 15 formed thereon, that is, a portion sandwiched by theN⁺ reverse conductive-type layer 14 and the N base layers 12, 13.

The basic operation of the IGBTs104, 104 a is the same as that of theIGBTs102, 102 a, 103, 103 a in accordance with the second or thirdpreferred embodiment. However, in the IGBTs102, 102 a, 103, 103 a, theN⁺ reverse conductive-type layer 14 is formed inside the P⁺ collectorlayer 11 with the result that the concentration of P-type impurities ofthe P⁺ collector layer 11 needs to be reduced to a low level incomparison with the conventional IGBTs151, 151 a. The resulting problemis that the amount of injection of holes from the P⁺ collector layer 11becomes low, causing the collector-emitter saturated voltage V_(CE(sat))to become higher. In contrast, in the IGBTs104, 104 a, since the P⁺diffusion layer 15 having a high concentration of impurities is formedin a region out of the P⁺ collector layer 11 in which no N⁺ reverseconductive-type layer 14 is formed; therefore, it is possible toincrease the amount of injection of holes from the P⁺ collector layer 11without impairing the function of N⁺ reverse conductive-type layer 14,and consequently to reduce the collector-emitter saturated voltageV_(CE(sat)).

When the IGBT104 is manufactured, upon completion of processes shown inFIG. 13 for manufacturing the IGBT102, as shown in FIG. 18, P-typeimpurities are implanted with a high concentration to a region out ofthe exposed surface of the P⁺ layer 11 in which no N⁺ reverseconductive-type layer 14 is formed, and diffused therein; thus, the P⁺diffusion layer 15 is formed. The P⁺ diffusion layer 15 is formed deeplyin a manner so as to form a junction to the N⁺ buffer layer. Theprocesses to be carried out thereafter are the same as the manufacturingprocesses of the IGBT102 after the processes of FIG. 13.

In the same manner, in the case of the manufacturing processes of theIGBT104 a, after the processes of FIG. 12 for manufacturing the IGBT102a, as shown in FIG. 19, P-type impurities are implanted with a highconcentration to a region out of the exposed surface of the P⁺ layer 11that has no N⁺ reverse conductive-type layer 14 formed thereon, anddiffused therein; thus, the P⁺ diffusion layer 15 is formed. The P⁺diffusion layer 15 is formed deeply in a manner so as to form a junctionto the N⁻ base layer 13. The processes to be carried out thereafter arethe same as the manufacturing processes of the IGBT102 a after theprocesses of FIG. 12.

As described above, the IGBTs104, 104 a are easily manufactured byadding a process for forming the P⁺ diffusion layer 15 to a method forforming the IGBTs102, 102 a, 103, 103 a.

5. Fifth Preferred Embodiment

FIG. 20 is a circuit diagram (in which 101 is typically added as areference number for an IGBT) of a semiconductor device using IGBTs101to 104, 101 a to 104 a as switching elements. This semiconductor device105 is formed as a three-phase inverter. Different from the conventionalsemiconductor device 152, the P⁺ collector layer 11 and the N baselayers 12, 13 have characteristics as a freewheel diode so that theIGBT101 itself is allowed to function as a freewheel diode in anequivalent manner; therefore, it is not necessary to connect a freewheeldiode 160 (FIG. 31) thereto in a separate manner. FIG. 20 also shows afreewheel diode in which the IGBT101 itself functions in an equivalentmanner.

The six IGBTs101 are series-connected two by two. A collector electrode8 of one of the series-connected two IGBTs101 is connected to a higherpotential power-supply terminal PP, and an emitter electrode 7 of theother is connected to a lower potential power-supply terminal NN. Thatis, three series circuits, each having the two IGBTs101, are connectedin parallel with each other between the higher potential power-supplyterminal PP and the lower potential power-supply terminal NN. Anexternal direct-current power-supply 20 is connected to the higherpotential power-supply terminal PP and the lower potential power-supplyterminal NN so that a direct current voltage is supplied thereto. Ineach of the series circuits, the connecting portion of the two IGBTs101series-connected is connected to any one of output terminals U, V, W.For example, a load 21 such as a three-phase motor is connected to thethree-phase output terminals U, V, W. Here, it is possible to form asingle phase inverter by removing one of the three series circuits fromthe semiconductor device 105 of FIG. 20.

Gate voltage V_(GE) is externally applied to six gate electrodes 5installed in the six IGBTs101 individually so that the six IGBTs101 areselectively turned on and off. Thus, an alternating current of threephases is supplied to the load 21. The following description willdiscuss this operation in detail.

When the IGBT101 connected to the higher potential power-supply terminalPP is turned on in one of the series circuits with the IGBT101 connectedto the lower potential power-supply terminal NN being turned on inanother series circuit, a direct current voltage supplied by thedirect-current power supply 20 is applied to the load 21. As a result,the current flowing through the load 21 gradually increases. When theseIGBTs101, which have been turned on, are turned off, a current of theload 21 tries to flow continuously by energy accumulated in an inductionL of the load 21, and flows through another IGBT101 that is seriesconnected to the IGBT101 that has been turned on, as a reverse current.

Since the IGBT101 has its reverse voltage resistance set low so as toexert the same functions as the freewheel diode 160, the current of theload 21 continues to flow without being abruptly interrupted. With thisarrangement, the load 21 is allowed to flow through the power supply 20in a reversed direction. Accordingly, the energy accumulated in theinduction L is gradually returned to the direct-current supply 20 sothat the current decreases gradually. Since the reverse voltageresistance of IGBT101 is low, it is possible to prevent the energyaccumulated in the induction L from being released to the IGBT101abruptly.

Therefore, the current of the load 21 can be controlled by on-offoperations of the IGBT101. In other words, an on-period and anoff-period of the IGBT101 are appropriately adjusted with the IGBT101being reciprocally turned on and off with a short cycle so that anaverage voltage to be applied to the load 21 is moderately changed in asine-wave form; thus, a current having a sine-wave form in accordancewith this sine-wave voltage and a power factor of the load 21 is allowedto flow. Since the load 21 such as a motor connected to an inverter hasa high power factor, a phase of the sine-wave voltage and a phase of thesine-wave current are made virtually coincident with each other.

For this reason, during the period in which the sine-wave voltagebecomes greatest, that is, the period in which the on-period ratio (theratio of on-period) is the greatest, the current is virtually maximized,and during the period in which the off-period ratio (the ratio ofoff-period, that is, the ratio of period in which a reverse currentflows through the IGBT101) is highest, the current is virtuallyminimized. Consequently, when these are time-averaged, the forwardcurrent, which flows through the IGBT101 when the IGBT101 is turned on,becomes not less than 5 times the reverse current that flows when theIGBT101 is turned off. In the IGBT101, the reverse voltage resistance isreduced to not more than 5 times the collector-emitter saturated voltageV_(CE(sat)); therefore, the semiconductor device 105 is allowed to avoiddamage to the IGBT101 while the structure for releasing loss heatgenerated in the IGBT101, that is, the heat-radiating structure, is thesame as the conventional semiconductor device 152, without the necessityof connection to the freewheel diode 160.

6. Sixth Preferred Embodiment

(Device Construction)

FIG. 21 is a plan view of a semiconductor device serving as an appliedapparatus of the IGBTs101 to 104, 101 a to 104 a (in which the IGBT101is typically shown). This semiconductor device 106 corresponds to apreferred specific structural example of the semiconductor device (thatis, a three-phase inverter) 105 of FIG. 20. Therefore, a circuit diagramof the semiconductor device 106 is given in FIG. 20. FIG. 22 is across-sectional view of the semiconductor device taken along a line A—Aof FIG. 21.

The semiconductor device 106 comprises a housing 30, a heat-radiatingplate 31 formed as one portion thereof, a substrate 35 placed on theheat-radiating plate 31, the six IGBTs101 placed on the substrate 35,the higher potential power-supply terminal PP, the lower potentialpower-supply terminal NN, the three output terminals U, V, W, the sixgate terminals G, a number of conductive wires w and a lid 33. Differentfrom the conventional semiconductor device 153 (FIGS. 32 and 33), nofreewheel diodes 160 are placed on the substrate 35.

The housing 30 (including the heat-radiating plate 31) and the lid 33cooperatively form a closed space 32, and the substrate 35 is mounted inthis closed space 32. Each of the higher potential power-supply terminalPP, the lower potential power-supply terminal NN, the three outputterminals U, V, W, and the six gate terminals G, is buried in thehousing 30 so that its upper end portion protrudes from an upper portionof the housing 30, and its lower end portion is exposed to the closedspace 32. The six IGBTs101 are connected to the eleven terminals PP, NN,U, V, W, G through a number of conductive wires w. The conductive wiresw are, for example, aluminum wires. Here, FIG. 21 shows thesemiconductor device 106 with its lid 33 being removed.

FIG. 23 is a plan view of the substrate 35, and FIG. 24 is across-sectional view taken along a cutting line B—B of FIG. 23. FIGS. 23and 24 simultaneously show the IGBT101 placed on the substrate 35. Thesubstrate 35 comprises an insulating plate 36 and wiring patterns 37placed thereon. The wiring pattern 37 is preferably made of copper asits major component. The insulating plate 36 is fixed on theheat-radiating plate 31 (FIG. 22), and the IGBT101 is mounted onto thewiring pattern 37, and electrically connected thereto. In this manner,each of the IGBTs101 is used in the form of bear chip.

The collector electrode 8 of each IGBT101 is connected to the wiringpattern 37. Moreover, the emitter electrode 7 of one of the two IGBTs101constituting a series circuit is connected to the higher potentialpower-supply terminal PP through the conductive wire w, and connectionsbetween the emitter electrode 7 of the other and any one of the threeoutput terminals U, V, W, between the collector electrodes 8 of the oneand any one of the three output terminals U, V, W, and between thecollector electrode 8 of the other and the lower potential power-supplyterminal NN are made through the wiring pattern 37 and the conductivewire w. Moreover, each of the gate electrodes 5 of the six IGBTs101 isconnected to the corresponding gate terminal G through the conductivewire w.

In the semiconductor device 106, since it is not necessary to installthe freewheel diode 160, it is possible to make the size of thesubstrate 35 small in comparison with the conventional semiconductordevice 153. This is clearly shown by the comparison between FIG. 34 andFIG. 23. Consequently, it is possible to further reduce the size of theentire semiconductor device 106 in comparison with the semiconductordevice 153. Moreover, as clearly shown by comparison between FIG. 21 andFIG. 32, in the semiconductor device 106, it is possible to reduce thenumber of conductive wires w in comparison with the semiconductor device153.

FIG. 25 is an inner perspective view of a semiconductor device thatshows another example of an applied apparatus. This semiconductor device107 comprises a heat-radiating plate 125, an IGBT101 (which typicallyshows the IGBT101 to 104, 101 a to 104 a), a collector terminal 41, anemitter terminal 42, a gate terminal 43, conductive wires w and asealing member 46 that seals all the elements except for the tipportions of the respective three terminals 41, 42, 43. A heat-radiatingplate 45, which is made of cupper, and also referred to as a cupperframe, serves as a reinforcing member and a wiring pattern as well.Different from the conductive semiconductor device 154, no freewheeldiode 160 is placed.

The collector electrode 8 of the IGBT101 is connected to the collectorterminal 41 through the heat-radiating plate 45. Connections between theemitter electrode 7 of the IGBT101 and the emitter terminal 42 andbetween the gate electrode 5 of the IGBT101 and the gate terminal 43 arerespectively made by the conductive wire w.

In the semiconductor device 107, since it is not necessary to installthe freewheel diode 160, it is possible to reduce the size of the entiresemiconductor device 106 in comparison with the conventionalsemiconductor device 154. Moreover, as clearly shown by comparisonbetween FIG. 25 and FIG. 35, in the semiconductor device 107, it ispossible to reduce the number of conductive wires w in comparison withthe semiconductor device 154.

(Manufacturing Method of the Device)

FIGS. 26 to 28 are manufacturing process drawings that show a method ofmanufacturing the semiconductor device 107. FIG. 28 is a cross-sectionalview taken along a cutting line C—C of FIG. 27 that shows anintermediate product. When the semiconductor device 107 is manufactured,first, the IGBT101 is obtained by executing a manufacturing method inaccordance with the first preferred embodiment. Simultaneously with thisprocess, a substrate 35 (FIG. 26) and a housing 30 (FIGS. 27 and 28) areprepared. In the substrate 35, wiring patterns 37 are placed on aninsulating plate 36. In the housing 30 with a heat-radiating plate 31placed on its bottom portion, various terminals PP, NN, U, V, W, G areburied.

Next, the IGBT101 is fixed onto the wiring pattern 37 of substrate 35.Successively, the substrate 35 on which the IGBTs101 are placed isadhered to the heat-radiating plate 31 corresponding to the bottom plateof the housing 30. Thus, the IGBTs101 and the substrate 35 are mountedin a closed space 32. Next, as described by reference to FIG. 21 andFIG. 22, the respective electrodes 5, 7, 8 of the IGBT101 and therespective terminals PP, NN, U, V, W, G of the housing 30 areelectrically connected through the conductive wires w. Then, byattaching the lid 33 to the upper portion of the housing 30, thesemiconductor device 106 is completed. A semiconductor device includinga direct-current power-supply 20 and/or a load 21 may be manufactured byconnecting the direct-current power-supply 20 and/or the load 21 to thesemiconductor device 106, and this may be shipped as a product.

When the semiconductor device 107 (FIG. 25) is manufactured, first, theIGBT101 is obtained by executing the manufacturing method in accordancewith the first preferred embodiment. Simultaneously with this process,the three terminals 41, 42, 43 and the heat-radiating plate 45 areprepared. The heat-radiating plate 45 is connected to the collectorterminal 42. Next, by fixing the IGBT101 onto the heat-radiating plate45, the collector electrode 8 of the IGBT101 is electrically connectedto the collector terminal 41. Next, the emitter electrode 7 of theIGBT101 is electrically connected to the emitter terminal 42 by usingthe conductive wires w, and the gate electrode 5 is electricallyconnected to the gate terminal 43. Thereafter, all the elements aresealed by a sealing member 46 except for a tip portion of each of thethree terminals 41, 42, 43, which externally protrudes from the sealingmember 46. The sealing member 46 is made of, for example, resin. Afterthe above-mentioned processes, the semiconductor device 107 iscompleted.

In the manufacturing processes of the semiconductor devices 106, 107, itis neither necessary to place the freewheel diodes 160, nor necessary toelectrically connect the freewheel diodes 160 to other portions;therefore, it is possible to further simplify the manufacturingprocesses in comparison with the manufacturing processes of theconventional semiconductor devices 153, 154. This fact is clearlyindicated by a reduction in the number of conductive wires w to be usedas well as a reduction in the number of processes used for attaching theconductive wires w. Thus, it becomes possible to reduce the size of thedevice and also to cut the manufacturing costs.

Modification

The above-mentioned preferred embodiments have been described byexemplifying N-channel-type IGBTs as IGBTs; however, this invention isof course applied to P-channel-type IGBTs.

While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

What is claimed is:
 1. An insulated gate bipolar transistor comprising:a semiconductor substrate having first and second major surfaces; acollector electrode which is located on said first major surface side ofsaid semiconductor substrate; and an emitter electrode and a gateelectrode that are located on said second major surface side, whereinsaid semiconductor substrate comprises: a collector layer of a firstconductive type that is exposed to said first major surface andconnected to said collector electrode; and a base layer of a secondconductive type that is formed on said collector layer and is notexposed to said first major surface, and wherein said base layer andsaid collector layer have a characteristic as a freewheel diode.
 2. Theinsulated gate bipolar transistor according to claim 1, wherein areverse voltage resistance, which is a minimum value of acollector-emitter voltage when a reverse current flows between saidemitter electrode and said collector electrode, is set to not more than5 times a collector-emitter saturated voltage.
 3. The insulated gatebipolar transistor according to claim 2, wherein said base layercomprises: a base main body portion; and a buffer layer that has ahigher concentration of impurities than said base main body portion andis interpolated between said collector layer and said base main bodyportion, and a minimum value of a collector-emitter voltage when anavalanche current flows through a parasitic diode formed by said baselayer and said collector layer is equivalent to said reverse voltageresistance.
 4. The insulated gate bipolar transistor according to claim2, wherein said semiconductor substrate further comprises: a reverseconductive-type layer of said second conductive type that is formedinside said collector layer so as not to be connected to said baselayer, and selectively exposed to said first major surface, andconnected to said collector electrode, and a minimum value of acollector-emitter voltage, that causes a punch through in which adepletion layer generated in a PN junction between said base layer andsaid collector layer reaches said reverse conductive-type layer, isequivalent to said reverse voltage resistance.
 5. The insulated gatebipolar transistor according to claim 4, wherein said collector layercomprises: a low impurity concentration collector layer; and a highimpurity concentration collector layer, said low impurity concentrationcollector layer comprises a portion of said collector layer sandwichedby said base layer and said reverse conductive-type layer, and said highimpurity concentration collector layer has a concentration of impuritieshigher than said low impurity concentration collector layer.
 6. Theinsulated gate bipolar transistor according to claim 2, wherein saidsemiconductor substrate further comprises: a reverse conductive-typelayer of said second conductive type that is formed inside saidcollector layer so as not to be connected to said base layer, andselectively exposed to said first major surface and connected to saidcollector electrode, and a minimum value of a collector-emitter voltagewhen a parasitic bipolar transistor formed by said base layer, saidcollector layer and said reverse conductive type layer turns on, isequivalent to said reverse voltage resistance.
 7. The insulated gatebipolar transistor according to claim 6, wherein said collector layercomprises: a low impurity concentration collector layer; and a highimpurity concentration collector layer, and said low impurityconcentration collector layer comprises a portion of said collectorlayer sandwiched by said base layer and said reverse conductive-typelayer, and said high impurity concentration collector layer has aconcentration of impurities higher than said low impurity concentrationcollector layer.
 8. The insulated gate bipolar transistor according toclaim 2, wherein said reverse voltage resistance is not more than 10 V.9. A semiconductor device comprising: the insulated gate bipolartransistor according to claim 1; a housing in which the insulated gatebipolar transistor is mounted; and three terminals each of which isattached to said housing with its one portion protruding from saidhousing toward the exterior, and which are electrically connected tosaid gate electrode, said emitter electrode and said collector electrodeof the insulated gate bipolar transistor, respectively.
 10. Thesemiconductor device according to claim 9, wherein said gate electrode,said emitter electrode and said collector electrode are electricallyconnected to said three terminals through conductive wires,respectively.
 11. The semiconductor device according to claim 9, furthercomprising: the insulated gate bipolar transistor serving as a firsttransistor; three insulated gate bipolar transistors having the samestructure as said first transistor and serving as second through fourthtransistors; said three-terminals serving as first to third terminals;and five terminals each of which is attached to said housing with oneportion thereof protruding from said housing toward the exterior, saidfive terminals serving as fourth to eighth terminals, wherein said firstand second transistors are series-connected, said third and fourthtransistors are series-connected, said first terminal is electricallyconnected to said collector electrodes of said first and thirdtransistors, said second terminal is electrically connected toconnecting sections of said first and second transistors, said thirdterminal is electrically connected to said gate electrode of said firsttransistor, said fourth terminal is electrically connected to saidemitter electrodes of said second and fourth transistors, said fifthterminal is electrically connected to connecting sections of said thirdand fourth transistors, and said sixth through eighth terminals areelectrically connected to said gate electrodes of said second throughfourth transistors, respectively.
 12. The semiconductor device accordingto claim 11, further comprising: an inductive load connected to saidsecond terminal and said fifth terminal.
 13. A semiconductor devicecomprising: the insulated gate bipolar transistor according to claim 1;a sealing member that seals the insulated gate bipolar transistor; andthree terminals each of which is sealed by said sealing member with oneportion thereof protruding from said sealing member toward the exterior,said three terminals electrically connected to said gate electrode, saidemitter electrode and said collector electrode of the insulated gatebipolar transistor, respectively.
 14. A manufacturing method of aninsulated gate bipolar transistor which comprises a semiconductorsubstrate having first and second major surfaces, a collector electrodethat is located on said first major surface side of said semiconductorsubstrate, and an emitter electrode and a gate electrode that arelocated on said second major surface side, comprising the steps of: (a)forming said semiconductor substrate so as to provide a collector layerof a first conductive type that is exposed to said first major surfaceand a base layer of a second conductive type that is formed on saidcollector layer and is not exposed to said first major surface; and (b)forming said collector electrode on said first major surface so as to beconnected to said collector layer, wherein in said step (a), saidsemiconductor substrate is formed so that said base layer and saidcollector layer are allowed to have a characteristic as a freewheeldiode.
 15. The manufacturing method of the insulated gate bipolartransistor according to claim 14, wherein in said step (a), saidsemiconductor substrate is formed in such a manner that a reversevoltage resistance, which is a minimum value of a collector-emittervoltage when a reverse current flows between said emitter electrode andsaid collector electrode, is set to not more than 5 times thecollector-emitter saturated voltage.
 16. The manufacturing method of theinsulated gate bipolar transistor according to claim 15, wherein in saidstep (a), said base layer comprises a base main body portion and abuffer layer that has a higher concentration in impurities than saidbase main body portion and is interpolated between said collector layerand said base main body portion, and said semiconductor substrate isformed so that a minimum value of a collector-emitter voltage when anavalanche current flows through a parasitic diode formed by said baselayer and said collector layer is equivalent to said reverse voltageresistance.
 17. The manufacturing method of the insulated gate bipolartransistor according to claim 15, wherein in said step (a), saidsemiconductor substrate further comprises a reverse conductive-typelayer of said second conductive type that is formed inside saidcollector layer so as not to be connected to said base layer, andselectively exposed to said first major surface, and connected to saidcollector electrode, and said semiconductor substrate is formed so thata minimum value of a collector-emitter voltage that causes a punchthrough in which a depletion layer generated in a PN junction betweensaid base layer and said collector layer reaches said reverseconductive-type layer is equivalent to said reverse voltage resistance.18. The manufacturing method of the insulated gate bipolar transistoraccording to claim 15, wherein in said step (a), said semiconductorsubstrate further comprises a reverse conductive-type layer of saidsecond conductive type that is formed inside said collector layer so asnot to be connected to said base layer, and selectively exposed to saidfirst major surface, and connected to said collector electrode, and saidsemiconductor substrate is formed so that a minimum value of acollector-emitter voltage when a parasitic bipolar transistor formed bysaid base layer, said collector layer and said reverse conductive typelayer turns on is equivalent to said reverse voltage resistance.